The present invention relates to a circuital arrangement for preventing latch-up phenomena in vertical PNP transistors with insulated collector.
As is known, in vertical PNP transistors with insulated collector, an N-type epitaxial well is present around the collector structure and must be connected to an appropriate voltage in order to avoid problems in the operation of said PNP transistor.
On this subject, reference should be made to FIG. 1, which is a transverse sectional view of a portion of a wafer of semiconductor material which integrates an insulated-collector PNP transistor. In this figure, the P-type substrate is indicated by 1, whereas 2 indicates the epitaxial layer, in which P-type insulation regions 3, which extend from the substrate to the main surface 4 of the device which integrates, among other devices, the PNP transistor, separate the well 2' from the other portions of the epitaxial layer. An N-type buried layer (a so-called "bottom N-well") 5 extends astride the substrate 1 and the epitaxial layer 2 (within the region delimited by the insulations 3), and the P-type collector layer 6 extends above the buried layer 5 and is connected to the main surface 4 of the device by means of a deep region 7, again of the P type, which extends in a ring-like shape and delimits a further well 2" of the epitaxial layer, which defines the base of the transistor.
A region 8 (which defines the so-called "top N-well") is indicated inside said second well 2", and an enhanced N-type region 10, at the base contact B, and the P-type emitter region 11 are formed therein.
The figure furthermore illustrates the emitter, base and collector contacts, respectively E, B and C, of the vertical PNP transistor, and a contact S for connecting the well 2' to an appropriate voltage; said contact is provided at an enhanced region which faces the main surface 4. FIG. 1 furthermore illustrates the electrical equivalents of some components which are the result of the illustrated structure, which comprises: the required vertical PNP transistor, which is indicated by 15 and is formed by the emitter layer 11, by the base layers 2", 8, 10 and by the collector layers 6, 7; a parasite NPN transistor 16 formed by the collector emitter 2", by the base layer 6 and by the emitter base 5; a parasite SCR 17, which is formed by the transistors 15 and 16; and a further parasite PNP transistor 18 formed by the emitter layer 6, the base layers 5 and 2' and the collector layer 1.
In order to prevent the parasite PNP transistor 18 from having an open base and to prevent the occurrence of unwanted latch-up phenomena affecting the SCR 17, due for example to voltage gradients (dV/dt) which can occur across it, it is therefore necessary to connect the N-well 2' to an appropriate voltage.
For this purpose, it has already been thought to connect the N-well 2', which also is the emitter of the parasite NPN transistor 16, to the emitter of the vertical PNP transistor, which is usually connected to the highest voltage (V.sub.cc), short-circuiting the contacts E and S. The equivalent electrical layout is shown in FIG. 2, in which only the vertical PNP transistor 15 and the parasite NPN transistor 16 have been illustrated for the sake of clarity.
However, although this solution is very simple and suitable for avoiding the latch-up of the SCR 17, it is not free from disadvantages, since the breakdown voltage which can be withstood between the emitter and the collector of the vertical transistor 15 is limited by the breakdown voltage of the junction formed by the layers 5 and 6 (i.e., by the breakdown of the base-emitter junction of the parasite NPN transistor 16, which, as is clearly illustrated in FIG. 2, by means of the indicated connection, is parallel-connected to the emitter-collector portion of the vertical PNP transistor 15).
This limitation does not create problems for low-voltage processes (up to 10 V), but is unacceptable in case of high-voltage processes.
Another solution consists in connecting the N-well 2' to the collector of the vertical PNP transistor 15 (connecting the contact S to the contact C), thus short-circuiting the base-emitter junction of the parasite NPN transistor 16. However, this solution entails only a local short-circuit, and in the presence of high currents, due to the drop on the collector layer 6, said base-emitter junction can become forward-biased, causing on the average the latch-up of the parasite SCR 17.